The NS electronic-design family

What is and is not installed

The latest plain declarations identify these base implementation groups:

The Basic declaration also lists a larger NS distribution: ns-routers, spice, drc, hp, timberwolf, compose, ns-doc, ns-tutorial, lsi-logic-support, vlsi-hacks, and several site/distribution files. Those names prove that the full product family could be larger. They do not prove that the missing systems are embedded in these five directories. A search of the purchased release and the locally decoded Help corpus found no installed NS documentation or tutorial payload at this boundary.

Four declarations also define separately issuable *-sources distribution recipes which enumerate expected .lisp names. That does not turn those names into source files in this release. The ordinary product systems set distribute-sources to false and distribute-binaries to true, and the inspected directories contain VBins instead. Basic's newer source recipe even names encrypted protection, basic-editor, and file-support inputs. The safe conclusion is “a separate source-delivery path was designed,” not “the purchased VBin set contains the source under another extension.”

PCB-NS also declares symbolics-part-number-data.bin in its source-distribution list, but the binary is absent from the inspected directory. Code for the part-number table remains, so the feature is present while the vendor data set is missing.

Libraries, modules, aspects, and diagrams

The central hierarchy is:

1. a library owns named modules, library options, technology choices, generators, and persistent definitions;
2. a module is a reusable design unit;
3. an aspect is one representation of a module, such as its schematic, icon, functional behavior, pinout, PC layout, virtual grid, mask, or floorplan;
4. a diagram holds editable objects and instances for a graphical aspect;
5. a buffer adds mode, selection, prior-mode state, view state, damage tracking, highlights, and temporary interaction state;
6. one or two views display the same or different buffers at independent centers and scales.

This model explains why “edit the schematic” and “edit the mask” are not separate launcher applications. They are aspect and mode changes within one editor. It also allows comparison and cross-selection: two views can show corresponding logical and physical representations while commands locate callers, signals, nodes, parts, or physical supports.

The compiled media names the following representation surface:

Frame and entry point

Compiled evidence: loading Basic-NS registers Select-S (ASCII 83) as “NS” and calls SELECT-NS-FRAME. The frame is a bordered constraint frame with a shared I/O buffer. It has four compiled configurations:

The BUCKYS pane is not decorative. Mouse motion updates documentation for the current modifier/button combination, making the dense chords discoverable. Basic-NS patches specifically repaired its highlighting, warm-boot behavior, X modifier handling, and mouse trackers on X displays. Other patches add initial color-X support and controller-specific color paths. These records establish that the interface evolved beyond a monochrome 3600-only prototype.

The interactor provides a Lisp command route beside pointing. The implementation also defines Dynamic Windows presentation types for libraries, modules, aspects, diagram instances, and related design objects. That makes typed object selection and command argument completion part of the design, even though the frame predates CLIM.

Menu button convention

Many NS menu items assign different meanings to the three buttons. The compiled documentation strings explicitly use [L], [M], and [R]:

That pattern is a semantic part of the interface. A later runtime study should not describe a menu item as a single action until all three button paths have been checked.

Complete compiled menu-action inventory

These 29 NEW-MENU-COMMAND registrations are distinct from the command-processor commands inventoried later. Other and Next are generic possibility-menu actions; the rest are named editor actions.

Next assigns left to next possibility, middle to previous, and right to a possibility menu. Define saves current diagram changes to a copy. Guts toggles all layout-cell interiors with left or right and one cell with middle. The exact visual presentation and ordering of these actions remains a runtime TODO.

View operations

Basic editing operations

Orientation, yank, and line tracking

The temporary tables are significant because the same chord changes meaning during a tracker. A static list of top-level bindings alone would not describe NS input accurately.

Picture and schematic modes

Picture mode inherits Basic and binds plain Middle to Line. Its Draw menu exposes Rectangle, Text, Circle, Ellipse, Arc, Arrow, and nested Picture construction in addition to lines. Schematic-Icon similarly binds Middle to a geometric line rather than an electrical wire.

Picture and Schematic both default to four-unit mouse quantization, ten-unit point/line proximity, twelve-unit short-line tolerance, twelve-unit text height, and ten-unit label height. Their selection-distance defaults differ: 20 for Picture and 32 for Schematic. These are compiled defaults, not runtime measurements of screen pixels.

RSIM mode

RSIM replaces most Basic bindings with node-oriented operations:

The compiled table alone does not explain the punctuation operations well enough to name their visible result. Their exact ? and ! behavior is therefore a runtime TODO, not guessed from punctuation convention.

PC-layout mode

The mode defines a point-grid display and derives its mouse quantization and grid spacing as one tenth of the PC-layout unit scale. Location reporting uses PC-layout units rather than the Basic buffer unit.

Floor-plan mode

The extremely large compiled selection-distance default (10000) appears deliberate for floorplan correspondence rather than a typo to silently normalize. Runtime confirmation of how it feels is still needed.

Mask mode

Mask mode uses four-unit mouse quantization, a sixteen-unit grid, four-unit maximum selection distance, and micron location reporting.

Virtual-grid mode

Virtual-grid mode uses a sixteen-unit quantization and grid, zero short-line tolerance, two-unit point/line proximity, sixteen-unit following distance, thirty-two-unit selection distance, and virtual-grid location units. Unlike Schematic, its “draw” chord is C-Middle because plain Middle constructs a log.

What it does

Basic-NS is both infrastructure and a usable picture editor. Its implementation provides:

• persistent libraries, modules, aspects, attributes, property descriptors, and generator definitions;
• editable primitive objects, points, lines, rectangles, text, circles, ellipses, arcs, arrows, and nested diagram instances;
• transformations, selection sets, connectivity selection, kill/yank history, movement, copying, rotation, mirroring, tracked drawing, and grid-snapped views;
• quad-tree spatial indexing and damaged-region redisplay;
• hierarchy navigation, callers and unused-module analysis, aspect comparison, and one- or two-view inspection;
• technology objects shared by PCB and IC extensions;
• color-aware rendering, cached drawing images, hardcopy, and Concordia integration;
• readable Lisp-oriented library definitions plus binary helper selection and file format converters.

The picture editor is more than a diagnostic canvas. It has commands to add a title frame and build slides, pie charts, bar graphs, and line graphs. Those builders are compiled product features; their exact visual styles are runtime TODOs.

Complete Basic command inventory

Install NS Password and the protected protection, basic, and file-support modules explain why media presence is not equivalent to a safely runnable editor. The system declaration calls out password protection explicitly. This article does not attempt to defeat it.

Data and persistence behavior

The implementation distinguishes human-oriented Lisp definitions from compiled helpers. A library can choose the newest Lisp or binary helper while preserving an explicit file type. Diagram “Define” saves changes as definitions rather than taking a memory snapshot; Save Diagrams and file-status commands operate at the aspect file level. Generated aspects, property descriptors, technologies, and generators are reconstructible definitions, while an editor buffer and its selection/history are transient state.

This means NS data is not analogous to a VM checkpoint. The library/module/aspect forms are design source in their own domain. Loading the VBins reconstructs program behavior, while loading design libraries reconstructs electronic objects. The two should not be collapsed into one “serialized image” category.

Schematic capture and icon construction

Schematic mode changes the default drawn segment from a generic line to an electrical wire and adds hierarchy- and node-oriented gestures. Its primitive menu contains passive components, sources, devices, and connectivity objects, including resistors, capacitors, inductors, transmission lines, voltage and current sources, controlled sources, pulse and piecewise-linear sources, MOSFET variants, input/output objects, bus widths, forks, and rippers. The exact icon artwork remains licensed compiled data and is not reproduced here.

Build Icon derives or edits a module's Schematic-Icon representation. Its compiled accept-values surface includes side-specific signal placement, aspect ratio, text and stub sizes, gate-input naming, and a DeMorgan option. Icon construction therefore is not merely drawing a rectangle around port names.

Network extraction

The extractor walks hierarchy and turns schematic objects into networks, nodes, devices, terminals, and paths. Source-visible checks cover:

• bus width and naming consistency;
• missing or ambiguous signal paths and repeated path iterations;
• global signals and hierarchy;
• selectable extraction environments;
• replacing a module with a schematic or functional-model aspect;
• device and terminal mappings, error highlighting, and correspondence back to visible objects.

Functional models use the shared Lisp object environment and four-state logic symbols 0, 1, X, and Z. The 1987 paper describes the same mixed strategy: schematic structure, behavioral Lisp, and extracted networks coexist in one data environment instead of passing only flat netlist files between isolated tools.

RSIM and waveform plots

RSIM is a switch-level simulator connected directly to schematic hierarchy. The compiled implementation preserves node value setting, watched-node and traced-node state, history, rename and capacitance explanation operations, hierarchy push/pop, simulation steps measured in tenths of a nanosecond, and plot aspects. A plot can add or remove nodes through the same pointer chords used from a schematic or RSIM view.

The 1987 paper independently describes mouse or Lisp control, value inspection, value forcing, stepping, hierarchy navigation, and mixed functional/switch-level simulation. It also mentions a hardware accelerator used in the original project. No accelerator is present in this Open Genera boundary, so its performance or availability is not inferred from the paper.

Electrical rules and timing analysis

Schematic ERC classifies drivers, consumers, direction, and tri-state behavior and marks errors in relation to design objects. The timing analyzer adds clocks, constraints, delay paths, critical-path analysis, ignored-path persistence, and incremental update. Source-visible support for changing transistor width and tracing functional-device clock constraints shows that it is connected to both schematic and device data.

Mach1000 support contains UNIX-server communication, a gate recognizer, and MIF generation. The server protocol is positive implementation evidence, but no matching server executable was found or run. Its operational status is therefore TODO.

Complete Schematic command inventory

The mouse-only RSIM operations in the preceding table are also user commands, but they are not duplicate command-processor registrations and are therefore not counted again here.

Design flow and aspect model

PCB-NS extends a logical schematic into several linked representations:

1. extract a PCB-oriented network from the schematic;
2. define Pin-Out and Electrical aspects for parts and pins;
3. assign physical packages and reference designators;
4. initialize or update the PC-Layout aspect;
5. place packages, inspect layers, and maintain the ratsnest;
6. swap equivalent gates or pins while propagating the change back to schematics;
7. run board electrical checks and simulation-related transformations;
8. generate reports and interchange files;
9. import external placement or swap changes through back annotation.

The PCB extractor can build a block diagram under PCB rules. A separate Hierarchicalize Schematic path raises global signals through hierarchy, rebuilds icons, and creates a form appropriate for board-level RSIM. Compiled references to PALCompiler show an integration point, but the corresponding product is not included among the five NS systems.

Pinout, packaging, and electrical data

Pin-Out aspects model package sections, physical pin numbers, common pins, NC pins, implicit power/ground, and gate/pin swap sets. Package assignment can be incremental, preserve fixed assignments, generate random reference designators for unresolved parts, and force layout updates.

The dedicated Pin-Out editor contains explicit limits: its compiled diagnostics say that shared pins and multiple gate types are not supported by that editor path. Other import/export code can represent some shared-pin and multi-section cases. This is a source-visible internal boundary, not a contradiction to erase.

Electrical aspects attach input/output direction, high/low current and loading, and logic-level data to pins and buses. PCB ERC uses those attributes to detect:

• floating pins and signals tied incorrectly to power or ground;
• multiple outputs, or problematic mixtures of output, tri-state, open-collector, and bidirectional drivers;
• nets with no receiver or no driver;
• missing pullups or ECL termination;
• logic-level incompatibilities;
• low- and high-state overload;
• grounded ECL inputs.

The implementation maintains sets of possible “next” checks, allows individual rules to be disabled, and relates reports back to schematic objects. It is not merely a batch text checker.

PC-layout editor and ratsnest

PC-Layout aspects contain the board outline, package icons, top and bottom layers, placement, grid, and relationship to the extracted PCB network. Commands initialize or update the layout from packaging, find off-grid icons, select icons corresponding to a schematic selection, set visible layers, and report layer visibility.

Ratsnest commands create, delete, or update connection guides for all or selected nodes and maintain an explicit no-ratsnest node set. The code checks package and layout validity before constructing it. Gate and pin swapping update both layout and schematic representations and honor the swap restrictions encoded in Pin-Out data.

Reports

Generate Report includes parts lists, package summaries and area, pin lists, wire lists, and bills of material. Find Ref-Des locates a reference designator in the linked design. Symbolics Part Number and Revert Part Number Table remain command registrations, but the separately declared vendor part-number data file is missing, so results which depend on that table are TODO.

SCICARDS, Cadnetix, and EDIF

The production interface is broader than a generic “netlist export”:

The Cadnetix writer has an indentation option. Its prompt says compact output is roughly 25 percent smaller for the expected files. That is a product estimate, not a universal property of EDIF.

Compiled defaults name standard PCB library categories for connectors, discrete parts, ECL, interface parts, LSI, PLD, RAM, ROM, and TTL. The associated library files were not separately verified, so these are installed-path expectations rather than a redistributable cell-library inventory.

Complete PCB command inventory

Device and technology layer

VLSI-NS adds IC-oriented primitives and technology objects to the schematic/network substrate. The compiled primitive definitions cover MOS devices, terminals, contacts, resistive and source elements, and SPICE attributes. Technology objects hold micron/lambda conversion, named layers and CIF names, legal contacts, minimum dimensions and overhangs, compactor and DRC parameters, MOS process corners, parasitics, and model constants.

The patch history is substantive historical evidence. Version 36 refined contact specifications, technology accessors, complex-contact checking, derived DRC layers, MOS size conversion, RSIM resistance, graph-compactor transforms, and mask creators. This is not a dormant demo accidentally shipped with Genera.

Virtual-grid layout

Virtual Grid is a symbolic IC-layout representation. It works with grid-aligned logs, contacts, supports, rectangles, transistors, ports, and terminals; records which layers connect; can add or remove X/Y grid structure; imports ports, including buses; toggles internal “guts”; and extracts a network for comparison or checking.

Source-visible checks include floating terminals, illegal overlaps, power/ground shorts, wrong well contacts, contact adequacy, and physical support. Path Under and connect/disconnect gestures make topology, not merely appearance, part of the editing model.

Mask layout

Mask mode edits physical rectangles, terminals, contacts, and P/N transistor geometry on named process layers. It supports visible and selectable layer sets, micron-oriented location display, hierarchy, creator matching, and constraint inspection. Some extraction and checking paths call separately distributed DRC or Compose facilities. Because those systems are absent, VLSI-NS media presence alone does not establish a complete physical verification flow.

Compaction and pitch matching

The media contains two compaction generations: the older Compact implementation and a constraint-graph compactor exposed as Gcompact. The latter can preprocess a layout, show a constraint graph, inspect constraints on selected objects, report unresolved constraints, reveal a critical path, and construct a symbolic stand-in. Pitch matching adjusts compatible layout dimensions or terminals. A right-button compactor tools path is also present in Mask mode.

The 1987 paper describes the same broad method: designers make structured datapaths or generators by hand, use symbolic layout and compaction, and retain explicit control over important regular structures. The released command and diagnostic surface is richer than the paper's overview.

Floorplanning

Floor-Plan aspects use slicing hierarchy, dividers, terminals, and ports. Compiled parameters include placement and routing-related choices and Ivory-specific design options. They prove the existence of a floorplanning representation, not that a complete automatic place-and-route system is installed. NS-Routers and Timberwolf are named in the wider distribution manifest but absent here.

Network comparison and electrical checks

Network Compare compares extracted networks from any two aspects. The code can match designs without relying solely on node names, check ports and devices, compare transistor sizes, and highlight suspects while using two views for correspondence. It is a bridge between logical and physical design, not a textual diff.

Transistor ERC checks ratio and topology conditions including keepers, transmission gates, and path lengths. Mask-oriented checks include power-consumption analysis and port consistency. The exact technology-specific thresholds depend on selected technology objects and are not generalized here.

SPICE and analog plots

The SPICE interface can:

• make local or remote runs;
• configure DC, AC, and transient analyses;
• select process corners and diffusion parasitics;
• generate a deck and retain input/output buffers;
• plot node voltage or source current;
• compare schematic and layout networks before using extracted parasitics;
• dispatch to a Chaos SPICE server or an HSPICE server.

Patch 36.23 adds explicit Chaos-versus-HSPICE remote dispatch and HSPICE options. Patch 36.24 incorporates the SPICE Delay Path implementation. Spice Delay Path turns a selected timing path into a generated schematic suitable for analog delay analysis.

The separately declared Spice system is absent from the five-system media, and no server was run. The command surface and protocol are established; a successful simulation in this preserved environment is not.

Complete VLSI command inventory

The mode gestures Set Layer, Describe Constraint, Find Vertical Constraint, Find Horizontal Constraint, What Layer, Match Creator, Compactor Tools Menu, Connect, Disconnect, Path Under, grid add/remove, and Import Ports are part of the user-visible command surface even though they are not separate command-processor registrations.

Hierarchical schematic and digital verification

Library / Module
      |
      +--> Schematic <--> Schematic-Icon
                |
                +--> extracted hierarchical network
                         |
                         +--> schematic ERC
                         +--> functional models + RSIM
                         +--> RSIM plot aspects
                         +--> timing analysis and critical paths

Gate-array estimation

Schematic network
      |
      +--> rule/technology mapping
      +--> gate-array count and utilization report
      +--> statistical wire capacitance annotation
      +--> updated timing/simulation data

Printed-circuit-board flow

Schematic network
      |
      +--> Pin-Out + Electrical aspects
      +--> package assignment / reference designators
      +--> PC-Layout placement + ratsnest + swaps
      +--> PCB ERC and reports
      +--> SCICARDS / Cadnetix EDIF
                     |
                     +--> external placement or editing
                     +--> Cadnetix / SCICARDS back annotation

Integrated-circuit flow

Schematic / functional model
      |
      +--> RSIM and timing analysis
      +--> Virtual-Grid symbolic layout
      |         |
      |         +--> compaction / pitch matching
      |         +--> network extraction
      +--> Mask physical layout
      +--> Floor-Plan
      |
      +--> network compare, transistor ERC, power checks
      +--> SPICE deck / remote run / plots

The shared objects are the architectural point. A selected timing path can become a SPICE schematic; a physical node can be matched back to another aspect; a PCB swap can update a schematic; a layout network can be compared to its logical source.

What System 46 preserves

The public System 46 tree contains 324 .DRW files totaling 4,776,539 bytes and 86 .PLT files totaling 669,231 bytes. Its README identifies them as SUDS material and says the surviving drawings appear to be CADR4 schematics; it also records that one Chaosnet-board SUDS file may have been lost from a damaged tape. The museum's visual-assets inventory records the exact census and rights boundary.

System 46 also contains the public DPLT renderer. It reads 36-bit SUDS .PLT streams in two passes, decodes vectors, text, and diamond records, finds bounds, rotates/scales the result, adds a frame/title, and writes Press output for a Dover printer. It explicitly does not support rotated characters, pads, and some PC-related material. DPLT is a plot consumer, not the SUDS editor.

What System 303 preserves

The LM-3 tree retains an evolved io1/dplt.lisp with bounding-box-aware versions, richer SUDS font mapping and styles, and an additional path for text reports. It also retains eight documentation .DRW files but no companion .PLT exports for those eight at the pinned check-in. The complete SUDS drawing editor is still absent.

Two LM-3 site declarations can look relevant by name but do not close the gap:

• site/amord.system registers an external AMORD rule/TMS tree on an OZ host;
• site/spice-plot.system registers external structures, window, parse-spice, plot, and random files on another OZ path.

Those declarations establish historical integration points only. Their external trees are not in the public checkout, and neither declaration is Symbolics NS.

Safe historical conclusion

SUDS proves that structured electronic drawings and Lisp-machine plot tooling predate the preserved NS release. NS proves that Symbolics later shipped an integrated schematic, simulation, PCB, gate-array, and IC environment. The inspected evidence does not prove that NS is a port, rewrite, or direct descendant of SUDS. Shared subject matter and three-button graphical editing are insufficient lineage evidence.